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fpga synthesis and post-placement optimizations.
ddr memory controllers and interfaces.
debugging tools, flows, and methodologies.
valavan manohararajah, gordon r. chiu, deshanand p. singh, stephen d. brown: predicting interconnect delay for physical synthesis in fpga cad flow. ieee transactions on very large scale integration systems, volume 15 number 8.
gordon r. chiu, deshanand p. singh, valavan manohararajah, stephen d. brown: mapping arbitrary logic functions into synchronous embedded memories for area reduction on fpgas. iccad 2006: pp. 135-142.
valavan manohararajah, gordon r. chiu, deshanand p. singh, stephen d. brown: difficulty of predicting interconnect delay in a timing driven fpga cad flow. slip 2006: 3-8.
issued us patents #7412677, #7444613, #7500216, and us patent application #20060129993.
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