fpga synthesis and post-placement optimizations.
ddr2/3 memory controllers and interfaces.
debugging tools, flows, methodologies.
gordon r. chiu, deshanand p. singh, valavan manohararajah, stephen d. brown: mapping arbitrary logic functions into synchronous embedded memories for area reduction on fpgas. iccad 2006: pp. 135-142.
valavan manohararajah, gordon r. chiu, deshanand p. singh, stephen d. brown: predicting interconnect delay for physical synthesis in fpga cad flow. ieee transactions on very large scale integration systems, volume 15 number 8.
issued us patents #7412677, #7444613, #7500216, #7620925, #7797666, #7821295, and us patent application #20060129993.